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Features
* * * * * * * * * * * *
80C51 Core Architecture 256 Bytes of On-chip RAM 1-Kbyte of On-chip ERAM 32K bytes of On-chip Flash Memory - Data Retention: 10 Years at 85C - Read/Write Cycle: 10k 2K Bytes of On-chip Flash for Bootloader 2K Bytes of On-chip EEPROM - Read/Write Cycle: 100k 14-sources 4-level Interrupts Three 16-bit Timer/Counters Full Duplex UART Compatible 80C51 Maximum Crystal Frequency 40 MHz - In X2 Mode, 20 MHz (CPU Core, 40 MHz) Five Ports: 32 + 2 Digital I/O Lines Five-channel 16-bit PCA with: - PWM (8-bit) - High-speed Output - Timer and Edge Capture Double Data Pointer 21-bit WatchDog Timer (Seven Programmable Bits) 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs On-chip Emulation Logic (Enhanced Hook System) Power Saving Modes: - Idle Mode - Power down Mode Power Supply: 5V 10% (or 3V* 10%) Temperature Range: Industrial (-40 to +85C) Packages: TQFP44, PLCC44 * Ask for availability
Enhanced 8-bit MCU with A/D Converter and 32K bytes Flash Memory
* * * * * * * *
T89C51AC2
Note:
Description
The T89C51AC2 is a high performance Flash version of the 80C51 single chip 8-bit microcontrollers. It contains a 32K byte Flash memory block for program and data. The 32K byte Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C51AC2 retains all features of the 80C51 with 256 bytes of internal RAM, a 7source 4-level interrupt controller and three timer/counters. In addition, the T89C51AC2 has a 10-bit A/D converter, a 2K bytes Boot Flash memory, 2-Kbyte EEPROM for data, a Programmable Counter Array, an ERAM of 1024 bytes, a Hardware WatchDog Timer, a nd a more versatile seria l channe l th at facilitates multiprocessor communication (EUART). The fully static design of the T89C51AC2 reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51AC2 has twosoftware-selectable modes of reduced activity and an 8-bit clock prescaler for further reduction in power consumption. In the idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabilities such as industrial control, consumer goods, alarms, motor control, among others.
Rev. 4127C-8051-04/02
While remaining fully compatible with the 80C52, the T8C51AC2 offers a superset of this standard microcontroller. In X2 mode, a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
Block Diagram
T2EX RxD TxD Vcc Vss PCA ECI T2 10 bit A-C
XTAL1 XTAL2 ALE PSEN CPU EA RD WR Timer 0 Timer 1 INT Ctrl Parallel I/O Ports and Ext. Bus Watch Dog Port 0 Port 1 Port 2 Port 3 Port 4 Emul Unit UART RAM 256x8
C51 CORE
Flash Boot EE 32kx loader PROM 8 2kx8 2kx8
ERAM
1kx8
PCA
Timer2
IB-bus
P1(1)
RESET
INT0
Notes:
1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port
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INT1
P4(2)
P2
T0
T1
P0
P3
T89C51AC2
Pin Configuration
P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PLCC44
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P2.0/A8
44 43 42 41 40 39 38 37 36 35 34
P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2
P4.0 P4.1 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9
P3.6/WR P3.7/RD
18 19 20 21 22 23 24 25 26 27 28
P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
TQFP44
ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 P0.0 /AD0 P2.0/A8
12 13 14 15 16 17 18 19 20 21 22 P3.6/WR P3.7/RD P4.0 P4.1 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9
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Table 1. Pin Description
Pin Name VSS VCC VAREF VAGND P0.0:7 I/O Type GND Description Circuit ground Supply Voltage Reference Voltage for ADC Reference Ground for ADC Port 0: Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1's written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application, it uses strong internal pull-ups when emitting 1's. Port 0 also outputs the code bytes during program validation. External pull-ups are required during program verification. Port 1: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1's written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, see "Electrical Characteristics" section) because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O. P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2. P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2. P1.2/AN2/ECI Analog input channel 2, PCA external clock input. P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output. P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output. P1.5/AN5/CEX2 Analog input channel 5, PCA module 2 Entry of input/PWM output. P1.6/AN6/CEX3 Analog input channel 6, PCA module 3 Entry of input/PWM output. P1.7/AN7/CEX4
P1.0:7
I/O
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Table 1. Pin Description (Continued)
Pin Name P2.0:7 Type I/O Description Port 2: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1's written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, see "Electrical Characteristics" section) because of the internal pull-ups. Port 2 emits the high-order address byte during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1's. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. It can drive CMOS inputs without external pull-ups. Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1's written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2/INT0: External interrupt 0 input/timer 0 gate control input P3.3/INT1: External interrupt 1 input/timer 1 gate control input P3.4/T0: Timer 0 counter input P3.5/T1: Timer 1 counter input P3.6/WR: External Data Memory write strobe; latches the data byte from port 0 into the external data memory P3.7/RD: External Data Memory read strobe; Enables the external data memory. P4.0:1 I/O Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1's written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. P4.0 P4.1: It can drive CMOS inputs without external pull-ups.
P3.0:7
I/O
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Table 1. Pin Description (Continued)
Pin Name RESET Type I/O Description Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are executed from an internal Flash (EA = 1), ALE generation can be disabled by the software. PSEN: The Program Store Enable output is a control signal that enables the external program memory of the bus during external fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when executing from of the external program memory two activations of PSEN are skipped during each access to the external Data memory. The PSEN is not activated for internal fetches. EA: When External Access is held at the high level, instructions are fetched from the internal Flash when the program counter is less then 8000H. When held at the low level,T89C51AC2 fetches all instructions from the external program memory. XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2: Output from the inverting oscillator amplifier.
ALE
O
PSEN
O
EA
I
XTAL1
I
XTAL2
O
I/O Configurations
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.
Port 1, Port 3 and Port 4
Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive. To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in "Section "Quasi-bi-directional Port Operation", page 9.
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Figure 1. Port 1, Port 3 and Port 4 Structure
VCC ALTERNATE OUTPUT FUNCTION
INTERNAL PULL-UP (1)
READ LATCH
INTERNAL BUS WRITE TO LATCH
D P1.X Q P3.X P4.X LATCH CL
P1.x P3.x P4.x
READ PIN
ALTERNATE INPUT FUNCTION
Note:
The internal pull-up can be disabled on P1 when analog function is selected.
Port 0 and Port 2
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to turn off the output driver FET. Figure 2. Port 0 Structure
ADDRESS LOW/ CONTROL DATA
VDD
(2)
READ LATCH
P0.x
1
(1)
INTERNAL BUS WRITE TO LATCH
D
P0.X LATCH
Q
0
READ PIN
Notes:
1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.
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Figure 3. Port 2 Structure
ADDRESS HIGH/ CONTROL VDD INTERNAL PULL-UP (2)
READ LATCH
1
P2.x
INTERNAL BUS WRITE TO LATCH D Q
0
(1)
P2.X LATCH
READ PIN
Notes:
1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line.
Read-Modify-Write Instructions
Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "ReadModify-Write" instructions. Below is a complete list of these special instructions (see Table 2). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: Table 2. Read-Modify-Write Instructions
Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y, C CLR Px.y SET Px.y Description logical AND logical OR logical EX-OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit y of Port x clear bit y of Port x set bit y of Port x Example ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P2 DEC P2 DJNZ P3, LABEL MOV P1.5, C CLR P2.4 SET P3.3
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T89C51AC2
It is not obvious that the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor's base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.
Quasi-bi-directional Port Operation
Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bi-directional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bi-directional " pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch.
Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-ModifyWrite instruction cycle.
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pullup (p1) to aid this logic transition (see Figure 4). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. Figure 4. Internal Pull-Up Configurations
2 Osc. PERIODS VCC p1(1) VCC p2 VCC p3 P1.x P2.x P3.x P4.x OUTPUT DATA n
INPUT DATA READ PIN
Note:
1. Port 2 p1 assists the logic-one output for memory bus cycles.
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SFR Mapping
The Special Function Registers (SFRs) of the T89C51AC2 fall into the following categories:
Table 3. C51 Core SFRs
Mnemonic ACC B PSW SP DPL Add Name 7 6 5 4 3 2 1 0
E0h Accumulator F0h B Register D0h Program Status Word 81h Stack Pointer 82h Data Pointer Low byte LSB of DPTR Data Pointer High byte MSB of DPTR CY AC F0 RS1 RS0 OV F1 P
DPH
83h
Table 4. I/O Port SFRs
Mnemonic P0 P1 P2 P3 P4 Add Name 7 6 5 4 3 2 1 0
80h Port 0 90h Port 1 A0h Port 2 B0h Port 3 C0h Port 4 (x2)
-
Table 5. Timers SFRs
Mnemonic TH0 TL0 TH1 TL1 TH2 TL2 TCON TMOD T2CON T2MOD RCAP2H Add Name 7 6 5 4 3 2 1 0
8Ch Timer/Counter 0 High byte 8Ah Timer/Counter 0 Low byte 8Dh Timer/Counter 1 High byte 8Bh Timer/Counter 1 Low byte CDh Timer/Counter 2 High byte CCh Timer/Counter 2 Low byte 88h Timer/Counter 0 and 1 control 89h Timer/Counter 0 and 1 Modes C8h Timer/Counter 2 control C9h Timer/Counter 2 Mode CBh Timer/Counter 2 Reload/Capture High byte Timer/Counter 2 Reload/Capture Low byte TF1 GATE1 TF2 TR1 C/T1# EXF2 TF0 M11 RCLK TR0 M01 TCLK IE1 GATE0 EXEN2 IT1 C/T0# TR2 IE0 M10 C/T2# T2OE IT0 M00 CP/RL2# DCEN
RCAP2L
CAh
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T89C51AC2
Table 5. Timers SFRs (Continued)
Mnemonic WDTRST WDTPRG Add Name 7 6 5 4 3 2 1 0
A6h WatchDog Timer Reset A7h WatchDog Timer Program S2 S1 S0
Table 6. Serial I/O Port SFRs
Mnemonic SCON SBUF SADEN SADDR Add Name 7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
98h Serial Control 99h Serial Data Buffer B9h Slave Address Mask A9h Slave Address
Table 7. PCA SFRs
Mnemo -nic CCON CMOD CL CH Add D8h D9h E9h F9h Name PCA Timer/Counter Control PCA Timer/Counter Mode PCA Timer/Counter Low byte PCA Timer/Counter High byte PCA Timer/Counter Mode 0 PCA Timer/Counter Mode 1 PCA Timer/Counter Mode 2 PCA Timer/Counter Mode 3 PCA Timer/Counter Mode 4 PCA Compare Capture Module 0 H PCA Compare Capture Module 1 H PCA Compare Capture Module 2 H PCA Compare Capture Module 3 H PCA Compare Capture Module 4 H PCA Compare Capture Module 0 L PCA Compare Capture Module 1 L PCA Compare Capture Module 2 L PCA Compare Capture Module 3 L PCA Compare Capture Module 4 L
CCAP0H7 CCAP1H7 CCAP2H7 CCAP3H7 CCAP4H7 ECOM0 ECOM1 ECOM2 ECOM3 ECOM4 CAPP0 CAPP1 CAPP2 CAPP3 CAPP4 CAPN0 CAPN1 CAPN2 CAPN3 CAPN4 MAT0 MAT1 MAT2 MAT3 MAT4 TOG0 TOG1 TOG2 TOG3 TOG4 PWM0 PWM1 PWM2 PWM3 PWM4 ECCF0 ECCF1 ECCF2 ECCF3 ECCF4
7
CF CIDL
6
CR WDTE
5
-
4
CCF4 -
3
CCF3 -
2
CCF2 CPS1
1
CCF1 CPS0
0
CCF0 ECF
CCAPM0 DAh CCAPM1 DBh CCAPM2 DCh CCAPM3 DDh CCAPM4 DEh CCAP0H FAh CCAP1H FBh CCAP2H FCh CCAP3H FDh CCAP4H FEh CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L EAh EBh ECh EDh EEh
CCAP0H6 CCAP1H6 CCAP2H6 CCAP3H6 CCAP4H6
CCAP0H5 CCAP1H5 CCAP2H5 CCAP3H5 CCAP4H5
CCAP0H4 CCAP1H4 CCAP2H4 CCAP3H4 CCAP4H4
CCAP0H3 CCAP1H3 CCAP2H3 CCAP3H3 CCAP4H3
CCAP0H2 CCAP1H2 CCAP2H2 CCAP3H2 CCAP4H2
CCAP0H1 CCAP1H1 CCAP2H1 CCAP3H1 CCAP4H1
CCAP0H0 CCAP1H0 CCAP2H0 CCAP3H0 CCAP4H0
CCAP0L7 CCAP1L7 CCAP2L7 CCAP3L7 CCAP4L7
CCAP0L6 CCAP1L6 CCAP2L6 CCAP3L6 CCAP4L6
CCAP0L5 CCAP1L5 CCAP2L5 CCAP3L5 CCAP4L5
CCAP0L4 CCAP1L4 CCAP2L4 CCAP3L4 CCAP4L4
CCAP0L3 CCAP1L3 CCAP2L3 CCAP3L3 CCAP4L3
CCAP0L2 CCAP1L2 CCAP2L2 CCAP3L2 CCAP4L2
CCAP0L1 CCAP1L1 CCAP2L1 CCAP3L1 CCAP4L1
CCAP0L0 CCAP1L0 CCAP2L0 CCAP3L0 CCAP4L0
Table 8. Interrupt SFRs
Mnemonic IEN0 IEN1 IPL0 IPH0 Add Name 7 EA 6 EC PPC PPCH 5 ET2 PT2 PT2H 4 ES PS PSH 3 ET1 PT1 PT1H 2 EX1 PX1 PX1H 1 ET0 EADC PT0 PT0H 0 EX0 PX0 PX0H
A8h Interrupt Enable Control 0 E8h Interrupt Enable Control 1 B8h Interrupt Priority Control Low 0 B7h Interrupt Priority Control High 0
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Table 8. Interrupt SFRs
Mnemonic IPL1 IPH1 Add Name 7 6 5 4 3 2 1 PADCL PADCH 0 -
F8h Interrupt Priority Control Low 1 F7h Interrupt Priority Control High1
Table 9. ADC SFRs
Mnemonic ADCON ADCF ADCLK ADDH ADDL Add Name 7 CH7 ADAT9 6 PSIDLE CH6 ADAT8 5 ADEN CH5 ADAT7 4 ADEOC CH4 PRS4 ADAT6 3 ADSST CH3 PRS3 ADAT5 2 SCH2 CH2 PRS2 ADAT4 1 SCH1 CH1 PRS1 ADAT3 ADAT1 0 SCH0 CH0 PRS0 ADAT2 ADAT0
F3h ADC Control F6h ADC Configuration F2h ADC Clock F5h ADC Data High byte F4h ADC Data Low byte
Table 10. Other SFRs
Mnemonic PCON AUXR AUXR1 CKCON FCON EECON Add Name 7 SMOD1 FPL3 EEPL3 6 SMOD0 WDX2 FPL2 EEPL2 5 M0 ENBOOT PCAX2 FPL1 EEPL1 4 POF SIX2 FPL0 EEPL0 3 GF1 XRS1 GF3 T2X2 FPS 2 GF0 XRS2 0 T1X2 FMOD1 1 PD EXTRAM T0X2 FMOD0 EEE 0 IDL A0 DPS X2 FBUSY EEBUSY
87h Power Control 8Eh Auxiliary Register 0 A2h Auxiliary Register 1 8Fh Clock Control D1h Flash Control D2h EEPROM Contol
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Table 11. SFR Mapping
0/8(1) F8h IPL1 xxxx x000 B 0000 0000 IEN1 xxxx x000 ACC 0000 0000 CCON 0000 0000 PSW 0000 0000 T2CON 0000 0000 P4 xxxx xx11 IPL0 x000 0000 P3 1111 1111 IEN0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8(1) TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR x00x 1100 CKCON 0000 0000 PCON 00x1 0000 7/F SBUF 0000 0000 SADDR 0000 0000 AUXR1 xxxx 00x0 WDTRST 1111 1111 WDTPRG xxxx x000 SADEN 0000 0000 IPH0 x000 0000 CMOD 00xx x000 FCON 0000 0000 T2MOD xxxx xx00 CCAPM0 x000 0000 EECON xxxx xx00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CCAPM1 x000 0000 CCAPM2 x000 0000 CCAPM3 x000 0000 CCAPM4 x000 0000 CL 0000 0000 1/9 CH 0000 0000 2/A CCAP0H 0000 0000 ADCLK xxx0 0000 CCAP0L 0000 0000 3/B CCAP1H 0000 0000 ADCON x000 0000 CCAP1L 0000 0000 4/C CCAP2H 0000 0000 ADDL 0000 0000 CCAP2L 0000 0000 5/D CCAP3H 0000 0000 ADDH 0000 0000 CCAP3L 0000 0000 6/E CCAP4H 0000 0000 ADCF 0000 0000 CCAP4L 0000 0000 IPH1 xxxx x000 7/F FFh
F0h
F7h
E8h
EFh
E0h
E7h DF h D7h CF h C7h
D8h
D0h
C8h
C0h
B8h
BFh
B0h
B7h
A8h
AFh
A0h
A7h
98h
9Fh
90h
97h
88h
8Fh
80h
87h
Reserved
Note: 1. These registers are bit-addressable. Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR's are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.
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Clock
The T89C51AC2 core needs only 6 clock periods per machine cycle. This feature, called"X2", provides the following advantages: * * * * Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency.
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System Programming".
Description
The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Table 5). The Timers 0, 1 and 2, Uart, PCA, or WatchDog switch in X2 mode only if the corresponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40% to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1/2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.
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Figure 5. Clock CPU Generation Diagram
X2B
Hardware byte On RESET PCON.0
IDL
X2
CKCON.0
XTAL1
/2
0 1
CPU Core Clock
XTAL2
CPU CLOCK
PD
PCON.1
CPU Core Clock Symbol and ADC /2 /2 /2 /2 /2
1
FT0 Clock
0
1
FT1 Clock
0
1
FT2 Clock
0
1 0
FUart Clock
1
FPca Clock
0
/2
1 0
FWd Clock
X2
CKCON.0
PERIPH CLOCK
Peripheral Clock Symbol WDX2
CKCON.6
PCAX2
CKCON.5
SIX2
CKCON.4
T2X2
CKCON.3
T1X2
CKCON.2
T0X2
CKCON.1
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Figure 6. Mode Switching Waveforms
XTAL1
XTAL2
X2 bit
CPU clock STD Mode X2 Mode STD Mode
Note:
In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.
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Register
Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register
7 Bit Number 6 WDX2 5 PCAX2 4 SIX2 3 T2X2 2 T1X2 1 T0X2 0 X2
Bit Mnemonic Description WatchDog clock(1)
6
WDX2
Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.
5
PCAX2
4
SIX2
3
T2X2
2
T1X2
1
T0X2
0
X2
Note:
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.
Reset Value = 0000 0000b
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Power Management
Two power reduction modes are implemented in the T89C51AC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in the Section "Clock". A reset is required after applying power at turn-on. To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running and stabilized and VCC established within the specified operating ranges. A device reset initializes the T89C51AC2 and vectors the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VDD as shown in Figure 7. Resistor value and input characteristics are discussed in the Section "DC Characteristics" of the T89C51AC2 datasheet. The status of the Port pins during reset is detailed in Table 13. Figure 7. Reset Circuitry and Power-On Reset
VDD
Reset
RST
R
To CPU core and peripherals
RST
+
RST
VSS
a. RST input circuitry
b. Power-on Reset
Table 13. Pin Conditions in Special Operating Modes
Mode Reset Idle Powerdown Port 0 Floating Data Data Port 1 High Data Data Port 2 High Data Data Port 3 High Data Data Port 4 High Data Data ALE High High Low PSEN# High High Low
Reset Recommendation to Prevent Flash Corruption
A bad reset sequence will lead to bad microcontroller initialization and system registers like SFR's, Program Counter, etc. will not be correctly initialized. A bad initialization may lead to unpredictable behavior of the C51 microcontroller. An example of this situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. If one wants the ENBOOT cleared inorder to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFR's may be set. If the value of Program Counter is accidently in the range of the boot memory addresses then a Flash access (write or erase) may corrupt the Flash on-chip memory . It is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage(power supply failure, power supply switched off).
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Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 13. To enter Idle mode, set the IDL bit in PCON register (see Table 14). The T89C51AC2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the T89C51AC2 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode.
Entering Idle Mode
Exiting Idle Mode
There are two ways to exit Idle mode: 1. Generate an enabled interrupt - Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51AC2 and vectors the CPU to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM.
2. Generate a reset -
Note:
Power-down Mode
The Power-down mode places the T89C51AC2 in a very low power state. Power-down mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 13.
Note: VDD may be reduced to as low as VRET during Power-down mode to further reduce power dissipation. Take care, however, that VDD is not reduced until Power-down mode is invoked.
Entering Power-down Mode
To enter Power-down mode, set PD bit in PCON register. The T89C51AC2 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed.
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Exiting Power-down Mode
There are two ways to exit the Power-down mode: 1. Generate an enabled external interrupt - The T89C51AC2 provides capability to exit from Power-down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 8). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode.
1. The external interrupt used to exit Power-down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. 2. Exit from Power-down by external interrupt does not affect the SFRs nor the internal RAM content. 3. If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is restored to the normal operating level.
Notes:
Figure 8. Power-down Exit Waveform Using INT1:0#
INT1:0#
OSC
Active phase
Power-down phase
Oscillator restart phase
Active phase
2. Generate a reset - A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51AC2 and vectors the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-down mode should not write to a Port pin or to the external RAM. 2. Exit from Power-down by reset redefines all the SFRs, but does not affect the internal RAM content.
Notes:
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Registers
PCON (S:87h) Table 14. PCON Register Power Configuration Register
7 Bit Number 7-4 6 5 4 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. General-purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. General-purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. Power-down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence.
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = XXXX 0000b
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Data Memory
The T89C51AC2 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: * * * the lower 128 bytes RAM segment. the upper 128 bytes RAM segment. the expanded 1024 bytes RAM segment (ERAM).
2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 10 shows the internal and external data memory spaces organization. Figure 9. Internal Memory - RAM
FFh Upper 128 bytes Internal RAM indirect addressing 80h 7Fh 80h Lower 128 bytes Internal RAM direct or indirect addressing FFh Special Function Registers direct addressing
00h
Figure 10. Internal and External Data Memory Organization ERAM-XRAM
FFFFh
64K bytes External XRAM
FFh or 3FFh 256 up to 1024 bytes Internal ERAM EXTRAM= 0 00h 0000h
EXTRAM= 1
Internal
External
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Internal Space
Lower 128 bytes RAM The lower 128 bytes of RAM (see Figure 10) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 17) select which bank is in use according to Table 15. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines. Table 15. Register Bank Selection
RS1 0 0 1 1 RS0 0 1 0 1 Description Register bank 0 from 00h to 07h Register bank 0 from 08h to 0Fh Register bank 0 from 10h to 17h Register bank 0 from 18h to 1Fh
The next 16 bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh. Figure 11. Lower 128 Bytes Internal RAM Organization
7Fh
30h 2Fh 20h 18h 10h 08h 00h 1Fh 17h 0Fh 07h 4 Banks of 8 Registers R0-R7 Bit-Addressable Space (Bit Addresses 0-7Fh)
Upper 128 bytes RAM
The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. The on-chip 1024 bytes of expanded RAM (ERAM) are accessible from address 0000h to 03FFh using indirect addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the XRAM. As shown in Figure 10 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is selected. The size of ERAM can be configured by XRS1-0 bit in AUXR register (default size is 1024 bytes).
Note: Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.
Expanded RAM
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External Space
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 12 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 16 describes the external memory interface signals. Figure 12. External Data Memory Interface Structure
T89C51AC2 A15:8 P2 ALE AD7:0 P0 Latch A7:0 A7:0 D7:0 RD# WR# OE WR A15:8 RAM PERIPHERAL
Table 16. External Data Memory Interface Signals
Signal Name A15:8 Type O Description Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. Read Read signal output to external data memory. Write Write signal output to external memory. Alternative Function P2.7 - 0
AD7:0
I/O
P0.7 - 0
ALE
O
-
RD#
O
P3.7
WR#
O
P3.6
External Bus Cycles
This section describes the bus cycles the T89C51AC2 executes to read (see Figure 13), and write data (see Figure 14) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode. Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and WR# signals from 3 to 15 CPU clock periods. For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section "AC Characteristics".
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Figure 13. External Data Read Waveforms
CPU Clock ALE RD#1 P0 P2
P2 DPL or Ri D7:0
DPH or P22
Notes:
1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Figure 14. External Data Write Waveforms
CPU Clock ALE WR#1 P0 P2
P2 DPL or Ri D7:0
DPH or P22
Notes:
1. WR# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
Dual Data Pointer
The T89C51AC2 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 19) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 15). Figure 15. Dual Data Pointer Implementation
DPL0 DPL1
DPTR0 DPTR1 0
DPL
1
DPS DPH0 DPH1
0
AUXR1.0
DPTR
DPH
1
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Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare...) are well served by using one data pointer as a "source" pointer and the other one as a "destination" pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes also advantage of this feature by providing enhanced algorithm libraries. The INC instruction is a short (2 bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.
; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added AUXR1EQU0A2h move:movDPTR,#SOURCE ; address of SOURCE incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST mv_loop:incAUXR1; switch data pointers movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address jnzmv_loop; check for NULL terminator end_move:
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Registers
Table 17. PSW Register PSW (S:8Eh) Program Status Word Register.
7 CY Bit Number 7 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 F1 0 P
Bit Mnemonic Description CY Carry Flag Carry out from bit 1 of ALU operands. Auxiliary Carry Flag Carry out from bit 1 of addition operands. User Definable Flag 0 Register Bank Select Bits Refer to Table 15 for bits description. Overflow Flag Overflow set by arithmetic operations. User Definable Flag 1 Parity Bit Set when ACC contains an odd number of 1's. Cleared when ACC contains an even number of 1's.
6 5 4-3
AC F0 RS1:0
2 1
OV F1
0
P
Reset Value = 0000 0000b Table 18. AUXR Register AUXR (S:8Eh) Auxiliary Register
7 Bit Number 7-6 6 5 M0 4 3 XRS1 2 XRS0 1 EXTRAM 0 A0
Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set this bit. Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0. M0 Pulse length in clock period 0 6 1 30
5
M0
4
-
Reserved The value read from this bit is indeterminate. Do not set this bit.
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Bit Number
Bit Mnemonic Description ERAM size: Accessible size of the ERAM XRS 1:0 ERAM size 0 0 256 bytes 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes (default) Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 0 - Internal ERAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access. Disable/Enable ALE) 0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 - ALE is active only during a MOVX or MOVC instruction.
3-2
XRS1-0
1
EXTRAM
0
A0
Reset Value = X00X 1100b Not bit addressable Table 19. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register 1
7 Bit Number 7-6 6 5 ENBOOT 4 3 GF3 2 0 1 0 DPS
Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. Enable Boot Flash Set this bit for map the boot Flash between F800h - FFFFh Clear this bit for disable boot Flash. Reserved The value read from this bit is indeterminate. Do not set this bit. General Purpose Flag 3 Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. Reserved for Data Pointer Extension Data Pointer Select Bit Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.
5
ENBOOT
4 3
GF3
2
0
1
-
0
DPS
Reset Value = XXXX 00X0b
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EEPROM Data Memory
The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth bit is set when writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row.
Write Data in the Column Latches
Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches: * * * * * * * Save and disable interrupt. Set bit EEE of EECON register Load DPTR with the address to write Store A register with the data to be written Execute a MOVX @DPTR, A If required, loop the three last instructions until the end of a 128 bytes page Restore interrupt.
The last page address used when loading the column latch is the one used to select the page programming address.
Note:
Programming
The EEPROM programming consists on the following actions: * Writing one or more bytes of one page in the column latches. Normally, all bytes must belong to the same page; if not, the first page address will be latched and the others discarded. Launching programming by writing the control sequence (50h followed by A0h) to the EECON register. EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading. The end of programming is indicated by a hardware clear of the EEBUSY flag.
The sequence 5xh and Axh must be executed without instructions between then otherwise the programming is aborted.
* * *
Note:
Read Data
The following procedure is used to read the data stored in the EEPROM memory: * * * * * Save and disable interrupt Set bit EEE of EECON register Load DPTR with the address to read Execute a MOVX A, @DPTR Restore interrupt
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Examples
;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM space
MOVX A, @DPTR MOV ret ;*F************************************************************************* ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 bytes. ;* before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_ld_eeprom_cl: MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ret EECON, #00h; unmap EEPROM
;*F************************************************************************* ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_wr_eeprom: MOV MOV ret EECON, #050h EECON, #0A0h
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Registers
Table 20. EECON Register EECON (S:0D2h) EEPROM Control Register
7 EEPL3 6 EEPL2 Bit Mnemonic EEPL3-0 5 EEPL1 4 EEPL0 3 2 1 EEE 0 EEBUSY
Bit Number 7-4
Description Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write in the column latches). Clear to map the XRAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software.
3
-
2
-
1
EEE
0
EEBUSY
Reset Value = XXXX XX00b Not bit addressable
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Program/Code Memory
The T89C51AC2 implement 32K bytes of on-chip program/code memory. Figure 16 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the Flash Memory can be programmed using only one voltage and allows InSystem Programming commonly known as ISP. Hardware programming mode is also available using specific programming tool. Figure 16. Program/Code Memory Organization
FFFFh
32K bytes external memory
8000h 7FFFh 32K bytes internal Flash EA = 1 0000h 0000h 7FFFh 32K bytes external memory EA = 0
Note:
If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper byte of on-chip memory (7FFFh) and thereby disrupt I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2.
External Code Memory Access
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 17 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21 describes the external memory interface signals.
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Figure 17. External Code Memory Interface Structure
T89C51AC2 P2 ALE P0 AD7:0 Latch A7:0 A7:0 D7:0 PSEN# OE A15:8 Flash EPROM A15:8
Table 21. External Code Memory Interface Signals
Signal Name A15:8 Type O Description Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. Program Store Enable Output This signal is active low during external code fetch or external code read (MOVC instruction). Alternate Function P2.7 - 0
AD7:0
I/O
P0.7 - 0
ALE
O
-
PSEN#
O
-
External Bus Cycles
This section describes the bus cycles the T89C51AC2 executes to fetch code (see Figure 18) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode see the "Clock" section. For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycling parameters refer to the "AC-DC parameters" section. Figure 18. External Code Fetch Waveforms
CPU Clock ALE PSEN# P0 D7:0 P2 PCH
PCL D7:0 PCL D7:0
PCH
PCH
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Flash Memory Architecture
T89C51AC2 features two on-chip Flash memories: * Flash memory FM0: containing 32K bytes of program memory (user space) organized into 128-byte pages, Flash memory FM1: 2K bytes for boot loader and Application Programming Interfaces (API).
*
The FM0 can be program by both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section. All Read/Write access operations on Flash Memory by user application are managed by a set of API described in the "In-System Programming" section. Figure 19. Flash Memory Architecture
2K bytes Flash memory boot space FM1
FFFFh
Hardware Security (1 byte) Extra Row (128 bytes) Column Latches (128 bytes)
F800h
7FFFh
32K bytes Flash memory user space FM0
FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register
0000h FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 19): 1. The memory array (user space) 32K bytes 2. The Extra Row 3. The Hardware security bits 4. The column latch registers User Space This space is composed of a 32K bytes Flash memory organized in 256 pages of 128 bytes. It contains the user's application code. This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage. The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from external memory is impossible.
Extra Row (XRow)
Hardware security Byte
Column latches
Cross Flash Memory Access Description
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The FM1 memory can be program only by parallel programming. The Table 22 show all software Flash access allowed. Table 22. Cross Flash Memory Access
Action Read Code executing from FM0 (user Flash) Load column latch Write Read FM1 (boot Flash) Load column latch Write External memory EA = 0 Read Load column latch Write FM0 (user Flash) ok ok ok ok ok FM1 (boot Flash) ok -
Overview of FM0 Operations
The CPU interfaces to the Flash memory through the FCON register and AUXR1 register. These registers are used to: * * * Map the memory spaces in the adressable space Launch the programming of the memory spaces Get the status of the Flash memory (busy/not busy)
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 23. A MOVC instruction is then used for reading these spaces. Table 23. FM0 Blocks Select Bits
FMOD1 0 0 1 1 FMOD0 0 1 0 1 FM0 Adressable Space User (0000h-FFFFh) Extra Row(FF80h-FFFFh) Hardware Security Byte (0000h) reserved
Launching Programming
The FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 24 summarizes the memory spaces to program according to FMOD1:0 bits.
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Table 24. Programming Spaces
Write to FCON FPL3:0 5 User A 5 Extra Row A Hardware Security Byte Reserved A X 1 1 No action 5 A 5 X X X X 0 1 1 1 1 0 0 1 X X 0 0 0 1 FPS X FMOD1 0 FMOD0 0 Operation No action Write the column latches in user space No action Write the column latches in extra row space No action Write the fuse bits space No action
Notes:
1. The sequence 5xh and Axh must be executing without instructions between them otherwise the programming is aborted. 2. Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the programming mode.
Status of the Flash Memory
The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress.
Selecting FM1 Loading the Column Latches
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Any number of data from 1-byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 20: * * * * * * Disable interrupt and map the column latch space by setting FPS bit. Load the DPTR with the address to load. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. If needed loop the three last instructions until the page is completely loaded. Unmap the column latch and Enable Interrupt
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Figure 20. Column Latches Loading Procedure
Column Latches Loading
Save and Disable IT EA= 0
Column Latches Mapping FCON = 08h (FPS = 1)
Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A
Last Byte to load?
Data memory Mapping FCON = 00h (FPS = 0)
Restore IT
Note:
The last page address used when loading the column latch is the one used to select the page programming address.
Programming the Flash Spaces User The following procedure is used to program the User space and is summarized in Figure 21: * * * Load up to one page of data in the column latches from address 0000h to 7FFFh. Disable the interrupts. Launch the programming by writing the data sequence 50h followed by A0h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared. Enable the interrupts.
* Extra Row
The following procedure is used to program the Extra Row space and is summarized in Figure 21: * * * Load data in the column latches from address FF80h to FFFFh. Disable the interrupts. Launch the programming by writing the data sequence 52h followed by A2h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared. Enable the interrupts. 37
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Figure 21. Flash and Extra row Programming Procedure
Flash Spaces Programming
Column Latches Loading see Figure 20
Save and Disable IT EA= 0
Launch Programming FCON= 5xh FCON= Axh
FBusy Cleared?
Clear Mode FCON = 00h
End Programming Restore IT
Hardware Security Byte
The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 22:
* * * * * * Set FPS and map Hardware byte (FCON = 0x0C) Save and disable the interrupts. Load DPTR at address 0000h. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. Launch the programming by writing the data sequence 54h followed by A4h in FCON register (only from FM1). The end of the programming indicated by the FBusy flag cleared. Restore the interrupts
*
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Figure 22. Hardware Programming Procedure
Flash Spaces Programming
Save and Disable IT EA= 0 Save and Disable IT EA= 0 Launch Programming FCON= 54h FCON= A4h
FCON = 0Ch
Data Load DPTR= 00h ACC= Data Exec: MOVX @DPTR, A
FBusy Cleared?
End Loading Restore IT
Clear Mode FCON = 00h
End Programming RestoreIT
Reading the Flash Spaces User The following procedure is used to read the user space: * Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR = read@.
FCON is supposed to be reset when not needed.
Note:
Extra Row
The following procedure is used to read the Extra Row space and is summarized in Figure 23: * * * Map the Extra Row space by writing 02h in FCON register. Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = FF80h to FFFFh. Clear FCON to unmap the Extra Row.
Hardware Security Byte
The following procedure is used to read the Hardware Security space and is summarized in Figure 23:
* * * Map the Hardware Security space by writing 04h in FCON register. Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = 0000h. Clear FCON to unmap the Hardware Security Byte.
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Figure 23. Reading Procedure
Flash Spaces Reading
Flash Spaces Mapping FCON= 00000xx0b
Data Read DPTR= Address ACC= 0 Exec: MOVC A, @A+DPTR
Clear Mode FCON = 00h
Flash Protection from Parallel Programming
The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 25 provide different level of protection for the onchip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode. They are set by default to level 4. Table 25. Program Lock Bit
Program Lock Bits Security level 1 LB0 LB1 LB2
Protection Description No program lock features enabled. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. Same as 2, also verify through parallel programming interface is disabled. Same as 3, also external execution is disabled if code roll over beyond 7FFFh
U
U
U
2
P
U
U
3
U
P
U
4
U
U
P
Program Lock bits U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be programmed after Flash and Core verification. Preventing Flash Corruption See paragraph in the Section "Power Management".
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Registers
Table 26. FCON Register FCON RegisterFCON (S:D1h) Flash Control Register
7 FPL3 Bit Number 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY
Bit Mnemonic Description Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 24). Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. Flash Mode See Table 23 or Table 24. Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software.
7-4
FPL3:0
3
FPS
2-1
FMOD1:0
0
FBUSY
Reset Value = 0000 0000b
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In-System Programming (ISP)
With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C51AC2 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product's life: * Before assembly the first personalization of the product by programming in the FM0 and if needed also a customized Boot loader in the FM1. Atmel also provides a standard Boot loader by default UART. After assembling on the PCB in its final embedded position by serial mode via the UART.
*
This In-System Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel also provides the customer all the needed Application-Programming-Interfaces (API) which are needed for the ISP. The API are also located in the Boot memory. This allow the customer to have a full use of the 32 K byte user memory.
Flash Programming and Erasure
There are three methods of programming the Flash memory: * The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the UART. API can be called also by user's bootloader located in FM0 at [SBV]00h. A further method exist in activating the Atmel boot loader by hardware activation. The FM0 can be programmed also by the parallel mode using a programmer.
* *
Figure 24. Flash Memory Mapping FFFFh
2K bytes IAP bootloader FM1
F800h
7FFFh
Custom Boot Loader [SBV]00h 32K bytes Flash memory FM0
FM1 mapped between F800h and FFFFh when API called
0000h
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Boot Process
Software Boot Process Example Many algorithms can be used for the software boot process. Before describing them, Below is the description of the different flags and bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 on parts delivered with bootloader programmed. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FFh (no user boot loader in FM0). - To read or modify this byte, the APIs are used. Extra Byte (EB) and Boot Status Byte (BSB): - These bytes are reserved for customer use. - To read or modify these bytes, the APIs are used. Hardware Boot Process At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the value of Boot Loader Jump Bit (BLJB). Further at the falling edge of RESET if the following conditions (called Hardware condition) are detected: * * * PSEN low, EA high, ALE high (or not connected). - After Hardware Condition the FCON register is initialized with the value 00h and the PC is initialized with F800h (FM1).
The Hardware condition makes the bootloader to be executed, whatever BLJB value is. If no hardware condition is detected, the FCON register is initialized with the value F0h. Check of the BLJB value. * * If bit BLJB = 1: User application in FM0 will be started at @0000h (standard reset). If bit BLJB = 0: Boot loader will be started at @F800h in FM1.
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Figure 25. Hardware Boot Process Algorithm
RESET
bit ENBOOT in AUXR1 register is initialized with BLJB.
Hardware
Hardware condition? No
Yes
ENBOOT = 1 PC = F800h FCON = 00h
ENBOOT = 0 PC = 0000h No
FCON = F0h
BLJB == 0 ? Yes ENBOOT = 1 PC = F800h
Software
Application in FM0
Boot Loader in FM1
Application Programming Interface
Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All APIs are describe in an documentation: "In-System Programing: Flash Library for T89C51AC2". This is available on the Atmel web site www.ateml.com.
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Table 27. List of API
API Call PROGRAM DATA BYTE PROGRAM DATA PAGE PROGRAM EEPROM BYTE ERASE BLOCK ERASE BOOT VECTOR (SBV) PROGRAM BOOT VECTOR (SBV) PROGRAM EXTRA BYTE (EB) READ DATA BYTE READ EEPROM BYTE READ FAMILY CODE READ MANUFACTURER CODE READ PRODUCT NAME READ REVISION NUMBER READ STATUS BIT (BSB) READ BOOT VECTOR (SBV) READ EXTRA BYTE (EB) PROGRAM X2 READ X2 PROGRAM BLJB READ BLJB Read the status bit Read the boot vector Read the extra byte Write the hardware flag for X2 mode Read the hardware flag for X2 mode Write the hardware flag BLJB Read the hardware flag BLJB Description Write a byte in Flash memory Write a page (128 bytes) in Flash memory Write a byte in Eeprom memory Erase all Flash memory Erase the boot vector Write the boot vector Write the extra byte
XROW Bytes
Table 28. XROW Mapping
Description Copy of the Manufacturer Code Copy of the Device ID#1: Family code Copy of the Device ID#2: Memories size and type Copy of the Device ID#3: Name and Revision Default Value 58h D7h F7h FFh Address 30h 31h 60h 61h
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Hardware Security Byte
Table 29. Hardware Security Byte
7 X2B Bit Number 6 BLJB 5 4 3 2 LB2 1 LB1 0 LB0
Bit Mnemonic Description X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. Boot Loader Jump Bit - 1: To start the user's application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. Reserved The value read from these bits are indeterminate. Lock Bits
7
X2B
6
BLJB
5-3 2-0
LB2:0
Default value after erasing chip: FFh
Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode.
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Serial I/O Port
The T89C51AC2 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: * * Framing error detection Automatic address recognition
Figure 26. Serial I/O Port Block Diagram
IB Bus
Write SBUF SBUF Receiver
Read SBUF
TXD
SBUF Transmitter Mode 0 Transmit
Load SBUF
RXD
Receive Shift register Serial Port Interrupt Request
RI
TI
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register. Figure 27. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI RI
Set FE bit if stop bit is 0 (framing error) SM0 to UART mode control SMOD1SMOD0 POF GF1 GF0 PD IDL
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register bit is set. The software may examine the FE bit after each reception to check for data errors. Once set, only software or a reset clears the FE bit. Subsequently received frames with valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 28. and Figure 29.).
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Figure 28. UART Timing in Mode 1
RXD Start bit RI SMOD0=X FE SMOD0 = 1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit
Data byte
Figure 29. UART Timing in Modes 2 and 3
RXD Start bit RI SMOD0= 0 RI SMOD0 = 1 FE SMOD0 = 1
D0
D1
D2
D3
D4
D5
D6
D7
D8 Ninth Stop bit bit
Data byte
Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in the hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address will the receiver set the RI bit in the SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If necessary, you can enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
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Given Address
Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don't-care bits (defined by zeros) to form the device's given address. The don't-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example:
SADDR0101 0110b SADEN1111 1100b Given0101 01XXb
Here is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b
Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don't-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don't care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don't-care bits, e.g.:
SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb
The use of don't-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b,
Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b
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For slaves A and B, bit 2 is a don't care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
Registers
Table 30. SCON Register SCON (S:98h) Serial Control Register
7 FE/SM0 Bit Number 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Bit Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Serial port Mode bit 0 (SMOD0 = 0) Refer to SM1 for serial port mode selection. Serial port Mode bit 1 SM0 SM1 Mode 0 0 Shift Register 0 1 8-bit UART 1 0 9-bit UART 1 1 9-bit UART
FE 7 SM0
6
SM1
Baud Rate FXTAL /12 (or FXTAL /6 in mode X2) Variable FXTAL /64 or FXTAL/32 Variable
5
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 28 and Figure 29 in the other modes.
4
REN
3
TB8
2
RB8
1
TI
0
RI
Reset Value = 0000 0000b Bit addressable
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Table 31. SADEN Register SADEN (S:B9h) Slave Address Mask Register
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description Mask Data for Slave Individual Address
Reset Value = 0000 0000b Not bit addressable Table 32. SADDR Register SADDR (S:A9h) Slave Address Register
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description Slave Individual Address
Reset Value = 0000 0000b Not bit addressable Table 33. SBUF Register SBUF (S:99h) Serial Data Buffer
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description Data sent/received by Serial I/O Port
Reset Value = 0000 0000b Not bit addressable
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Table 34. PCON Register PCON (S:87h) Power Control Register
7 SMOD1 Bit Number 7 6 SMOD0 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL
Bit Mnemonic Description SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. General purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. Power-down mode bit Cleared by hardware when reset occurs. Set to enter Power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode.
6
SMOD0
5
-
4
POF
3
GF1
2
GF0
1
PD
0
IDL
Reset Value = 00X1 0000b Not bit addressable
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Timer/Counters
The T89C51AC2 implements two general-purpose, 16-bit Timer/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 35) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows, it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is FPER/6, i.e. FOSC/12 in standard mode or FOSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is FPER/12, i.e. F OSC/24 in standard mode or FOSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle.
Timer/Counter Operations
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 30 to Figure 33 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 36) and bits 0, 1, 4 and 5 of TCON register (see Figure 35). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop the Timer/Counter before changing modes.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register
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(see Figure 30). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 30. Timer/Counter x (x= 0 or 1) in Mode 0(1)
see the "Clock" section
FTx CLOCK /6 0 1
THx (8 bits)
TLx (5 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx# GATEx
TMOD reg
TRx
TCON reg
Note:
1. See the "Clock" section
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 31). The selected input increments TL0 register.
Figure 31. Timer/Counter x (x= 0 or 1) in Mode 1(1)
See the "Clock" section
FTx CLOCK /6 0 1
THx (8 bits)
TLx (8 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx# GATEx
TMOD reg
TRx
TCON reg
Note:
1. See the "Clock" section
Mode 2 (8-bit Timer with AutoReload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 32). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register.
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Figure 32. Timer/Counter x (x= 0 or 1) in Mode 2(1)
FTx CLOCK /6 0 1
TLx (8 bits)
Overflow
TFx
TCON reg
Tx C/Tx#
TMOD reg
Timer x Interrupt Request
INTx# GATEx
TMOD reg
TRx
TCON reg
THx (8 bits)
Note:
1. See the "Clock" section
Mode 3 (Two 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 33). This mode is provided for applications requiring an additional 8bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
Figure 33. Timer/Counter 0 in Mode 3: Two 8-bit Counters (1)
FTx CLOCK /6 0 1
TL0 (8 bits)
Overflow
TF0
TCON.5
T0 C/T0#
TMOD.2
Timer 0 Interrupt Request
INT0# GATE0
TMOD.3
TR0
TCON.4
FTx CLOCK
/6
TH0 (8 bits) TR1
TCON.6
Overflow
TF1
TCON.7
Timer 1 Interrupt Request
Note:
1. See the "Clock" section
Timer 1
Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: * Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 30 to Figure 32 show the logical configuration for modes 0, 1, and 2. Timer 1's mode 3 is a hold-count mode. Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 36) and bits 2, 3, 6 and 7 of TCON register (see Figure 35). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions:
*
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overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). * * Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request. When Timer 0 is in mode 3, it uses Timer 1's overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. It is important to stop the Timer/Counter before changing modes.
* *
*
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Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 30). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 31). The selected input increments TL1 register. Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 32). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 34. Timer Interrupt System
TF0
TCON.5
Mode 1 (16-bit Timer)
Mode 2 (8-bit Timer with AutoReload)
Mode 3 (Halt)
Interrupt
Timer 0 Interrupt Request ET0
IEN0.1
TF1
TCON.7
Timer 1 Interrupt Request ET1
IEN0.3
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Registers
Table 35. TCON Register TCON (S:88h) Timer/Counter Control Register
7 TF1 Bit Number 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0
Bit Mnemonic Description Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0.
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Reset Value = 0000 0000b
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Table 36. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register
7 GATE1 Bit Number 6 C/T1# 5 M11 4 M01 3 GATE0 2 C/T0# 1 M10 0 M00
Bit Mnemonic Description Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. Timer 1 Mode Select Bits M11 M01 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1). (1) 1 1 Mode 3: Timer 1 halted. Retains count. Timer 0 Gating Control Bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. Timer 0 Counter/Timer Select Bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. Timer 0 Mode Select Bit Operating mode M10 M00 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0). (2) 1 1 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1's TR0 and TF0 bits.
7
GATE1
6
C/T1#
5
M11
4
M01
3
GATE0
2
C/T0#
1
M10
0
M00
1. 2.
Reloaded from TH1 at overflow. Reloaded from TH0 at overflow.
Reset Value = 0000 0000b
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Table 37. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description High Byte of Timer 0.
Reset Value = 0000 0000b Table 38. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description Low Byte of Timer 0.
Reset Value = 0000 0000b Table 39. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description High Byte of Timer 1.
Reset Value = 0000 0000b
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Table 40. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register
7 6 5 4 3 2 1 0
Bit Number 7-0
Bit Mnemonic Description Low Byte of Timer 1.
Reset Value = 0000 0000b
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Timer 2
The T89C51AC2 Timer 2 is compatible with Timer 2 in the 80C52. It is a 16-bit Timer/Counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table 41) and T2MOD register (See Table 43). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F T2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 includes the following enhancements: * * Auto-reload mode (up or down counter) Programmable clock-output
Auto-reload Mode
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table 43). Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 35. In this mode the T2EX pin controls the counting direction. When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when Timer 2 overflow or underflow, depending on the direction of the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution.
Figure 35. Auto-Reload Mode Up/Down Counter(1)
FT2 CLOCK :6 0 1
TR2
T2CON.2
CT/2
T2CON.1
T2 (DOWN COUNTING RELOAD VALUE) T2EX: FFh (8-bit) FFh
(8-bit)
1=UP 2=DOWN TOGGLE T2CONreg EXF2
TL2 (8-bit)
TH2 (8-bit)
TF2 T2CONreg
Timer 2 INTERRUPT
RCAP2L (8-bit)
RCAP2H (8-bit)
(UP COUNTING RELOAD VALUE)
Note:
1. See the "Clock" section.
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Programmable Clockoutput
In clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 36). The input clock increments TL2 at frequency FOSC /2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency depending on the system oscillator frequency and the value in the RCAP2H and RCAP2L registers:
FT2clock Clock - OutFrequency = ------------------------------------------------------------------------------------------4 x ( 65536 - RCAP2H RCAP2L ) For a 16 MHz system clock in x1 mode, Timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: * * * * * Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application. To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 36. Clock-Out Mode
FT2 CLOCK 0 1
TR2
T2CON.2
CT/2
T2CON.1
TL2 (8-bit)
TH2 (8-bit) OVERFLOW
RCAP2L RCAP2H (8-bit) (8-bit) T2 1 0 :2
C/T2 T2CON reg T2EX EXEN2 T2CON reg
T2OE T2MOD reg EXF2 T2CON reg Timer 2 INTERRUPT
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Registers
Table 41. T2CON Register T2CON (S:C8h) Timer 2 Control Register
7 TF2 Bit Number 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2#
Bit Mnemonic Description Timer 2 overflow Flag TF2 is not set if RCLK = 1 or TCLK = 1. Must be cleared by software. Set by hardware on Timer 2 overflow. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1. Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt is enabled. Must be cleared by software. Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for Timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if Timer 2 is not used to clock the serial port. Timer 2 Run control bit Clear to turn off Timer 2. Set to turn on Timer 2. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin). Timer 2 Capture/Reload bit If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2 = 1. Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
7
TF2
6
EXF2
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Reset Value = 0000 0000b Bit addressable
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Table 42. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register
7 Bit Number 7 6 5 4 3 2 1 T2OE 0 DCEN
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit Clear to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter.
6
-
5
-
4
-
3
-
2
-
1
T2OE
0
DCEN
Reset Value = XXXX XX00b Not bit addressable Table 43. TH2 Register TH2 (S:CDh) Timer 2 High Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description High Byte of Timer 2.
Reset Value = 0000 0000b Not bit addressable
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Table 44. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Low Byte of Timer 2.
Reset Value = 0000 0000b Not bit addressable Table 45. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description High Byte of Timer 2 Reload/Capture.
Reset Value = 0000 0000b Not bit addressable Table 46. RCAP2L Register RCAP2L (S:CAH) TIMER 2 REload/Capture Low Byte Register
7 Bit Number 7-0 6 5 4 3 2 1 0 -
Bit Mnemonic Description Low Byte of Timer 2 Reload/Capture.
Reset Value = 0000 0000b Not bit addressable
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T89C51AC2
WatchDog Timer
T89C51AC2 contains a powerful programmable hardware WatchDog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-out ranking from 16ms to 2s @Fosc = 12 MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a WatchDog Timer reset register (WDTRST) and a WatchDog Timer programming (WDTPRG) register. When exiting reset, the WDT is -by default- disable. To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST register no instruction in between. When the WatchDog Timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset
Note: When the WatchDog is enabled it is impossible to change its period.
Figure 37. WatchDog Timer
Fwd CLOCK / PS /6 CPU and Peripheral Clock
RESET WR
Decoder
Control WDTRST
Enable WDTPRG Fwd Clock 14-bit COUNTER 7-bit COUNTER
Outputs
-
-
-
-
-
2
1
0 RESET
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WatchDog Programming
The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 47. Machine Cycle Count
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Machine Cycle Count 214 - 1 215 - 1 216 - 1 217 - 1 218 - 1 219 - 1 220 - 1 221 - 1
To compute WD Time-out, the following formula is applied: F wd FTime - Out = -----------------------------------------------------------------14 Svalue 12 x ( ( 2 x 2 ) - 1)
Note: Svalue represents the decimal value of (S2 S1 S0)
The following table describes the computed Time-out value for FoscXTAL = 12 MHz in X1 mode Table 48. Time-out Computation
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Fosc = 12MHz 16.38 ms 32.77 ms 65.54 ms 131.07 ms 262.14 ms 524.29 ms 1.05 s 2.10 s Fosc = 16MHz 12.28 ms 24.57 ms 49.14 ms 98.28 ms 196.56 ms 393.12 ms 786.24 ms 1.57 s Fosc = 20MHz 9.82 ms 19.66 ms 39.32 ms 78.64 ms 157.28 ms 314.56 ms 629.12 ms 1.25 ms
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WatchDog Timer During Power down Mode and Idle
In Power down mode the oscillator stops, which means the WDT also stops. While in Power down mode, the user does not need to service the WDT. There are 2 methods of exiting Power down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power down mode. When Power down is exited with hardware reset, the WatchDog is disabled. Exiting Power down with an interrupt is significantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51AC2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. Table 49. WDTPRG Register WDTPRG (S:A7h) WatchDog Timer Duration Programming Register
7 Bit Number 7 6 5 4 3 2 S2 1 S1 0 S0
Register
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. WatchDog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. WatchDog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. WatchDog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2.
6
-
5
-
4
-
3
-
2
S2
1
S1
0
S0
Reset Value = XXXX X000b
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Table 50. WDTRST Register WDTRST (S:A6h Write only) WatchDog Timer Enable register
7 Bit Number 7 6 5 4 3 2 1 0 -
Bit Mnemonic Description WatchDog Control Value
Reset Value = 1111 1111b
Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences.
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T89C51AC2
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T89C51AC2
Programmable Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals: * * * * * * * * PCA clock frequency/6 (see the "Clock" section) PCA clock frequency/2 Timer 0 overflow External input on ECI (P1.2) rising and/or falling edge capture, software timer high-speed output pulse width modulator
Each compare/capture module can be programmed in any one of the following modes:
Module 4 can also be programmed as a WatchDog timer. see the "PCA WatchDog Timer" section. When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O.
PCA Component 16-bit Counter 16-bit Module 0 16-bit Module 1 16-bit Module 2 16-bit Module 3 16-bit Module 4 External I/O Pin P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4
PCA Timer
The PCA timer is a common time base for all five modules (see Figure 38). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 51) and can be programmed to run at: * * * * 1/6 the PCA clock frequency 1/2 the PCA clock frequency the Timer 0 overflow the input on the ECI pin (P1.2)
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Figure 38. PCA Timer/Counter
To PCA modules FPca/6 FPca/2 T0 OVF P1.2 CH CL 16 bit up/down counter overflow It
CIDL Idle
WDTE
CPS1 CPS0
ECF
CMOD 0xD9
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON 0xD8
The CMOD register includes three additional bits associated with the PCA. * * * The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the WatchDog function on module 4. The ECF bit which, when set, causes an interrupt and the PCA overflow flag CF in CCON register to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA timer and each module. * * * The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. The CF bit is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in CMOD register is set. The CF bit can only be cleared by software. The CCF0:4 bits are the flags for the modules (CCF0 for module0...) and are set by hardware when either a match or a capture occurs. These flags also can be cleared by software.
PCA Modules
Each one of the five compare/capture modules has six possible functions. It can perform: * * * * * * 16-bit Capture, positive-edge triggered 16-bit Capture, negative-edge triggered 16-bit Capture, both positive and negative-edge triggered 16-bit Software Timer 16-bit High Speed Output 8-bit Pulse Width Modulator.
In addition module 4 can be used as a WatchDog Timer.
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T89C51AC2
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T89C51AC2
Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. * * * The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. The PWM bit enables the pulse width modulation mode. The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled. The bit ECOM in CCAPM register when set enables the comparator function.
*
*
*
PCA Interrupt
Figure 39. PCA Interrupt System
CF PCA Timer/Counter CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON
Module 0
Module 1
To Interrupt
Module 2
Module 3
Module 4
ECF
CMOD.0
ECCFn
CCAPMn.0
EC
IEN0.6
EA
IEN0.7
PCA Capture Mode
To use one of the PCA modules in capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.
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Figure 40. PCA Capture Mode PCA Counter
CH (8bits) CL (8bits)
CEXn n = 0, 4
CCAPnH CCAPnL
CCFn CCON Reg 7 CCAPMn Register (n = 0, 4) 0CAP PnCAP Nn000 ECCFn 0
PCA Interrupt Request
16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.
Figure 41. PCA 16-bit Software Timer and High Speed Output Mode
PCA Counter CH CL (8 bits) (8 bits) Compare/Capture Module CCAPnL CCAPnH (8 bits) (8 bits) Match 16-Bit Comparator Enable CCFn CCON reg Toggle CEXn PCA Interrupt Request
7 "0" Reset Write to CCAPnL Write to CCAPnH "1"
ECOMn0 0 MATn TOGn0 ECCFn 0 CCAPMn Register (n = 0, 4) For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn.
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High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set. Figure 42. PCA High Speed Output Mode
CCON CF Write to CCAPnH Write to CCAPnL "0" "1" Reset PCA IT CCAPnH Enable 16 bit comparator CCAPnL Match CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8
CH
CL
CEXn
PCA counter/timer CCAPMn, n = 0 to 4 0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Pulse Width Modulator Mode
All PCA modules can be used as PWM outputs. The output frequency depends on the source for the PCA timer. All the modules will have the same output frequency because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than it, the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
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Figure 43. PCA PWM Mode CCAPnH
CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL
CCAPnL "0" CL < CCAPnL CL (8 bits) 8-Bit Comparator CEX CL >= CCAPnL "1"
ECOMn
CCAPMn.6
PWMn
CCAPMn.1
PCA WatchDog Timer
An on-board WatchDog timer is available with the PCA to improve system reliability without increasing chip count. WatchDog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a WatchDog. However, this module can still be used for other modes if the WatchDog is not needed. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. To hold off the reset, the user has three options: * * * periodically change the compare value so it will never match the PCA timer, periodically change the PCA timer value so it will never match the compare values, or disable the WatchDog by clearing the WDTE bit before a match occurs and then reenable it.
The first two options are more reliable because the WatchDog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
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PCA Registers
Table 51. CMOD Register CMOD (S:D9h) PCA Counter Mode Register
7 CIDL Bit Number 6 WDTE 5 4 3 2 CPS1 1 CPS0 0 ECF
Bit Mnemonic Description PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. WatchDog Timer Enable Clear to disable WatchDog Timer function on PCA Module 4, Set to enable it. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) Reserved The value read from this bit is indeterminate. Do not set this bit. Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt.
7
CIDL
6
WDTE
5
-
4
-
3
-
2
CPS1
1
CPS0
0
ECF
Reset Value = 00XX X000b
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Table 52. CCON Register CCON (S:D8h) PCA Counter Control Register
7 CF Bit Number 6 CR 5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0
Bit Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software. PCA Module 3 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software. PCA Module 2 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software. PCA Module 1 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. PCA Module 0 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software.
7
CF
6
CR
5
-
4
CCF4
3
CCF3
2
CCF2
1
CCF1
0
CCF0
Reset Value = 00X0 0000b
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Table 53. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n = 0..4)
7 CCAPnH 7 Bit Number 7-0 6 CCAPnH 6 5 CCAPnH 5 4 CCAPnH 4 3 CCAPnH 3 2 CCAPnH 2 1 CCAPnH 1 0 CCAPnH 0
Bit Mnemonic Description CCAPnH 7 High byte of EWC-PCA comparison or capture values -0
Reset Value = 0000 0000b Table 54. CCAPnL Registers CCAP0L (S:EAh) CCAP1L (S:EBh) CCAP2L (S:ECh) CCAP3L (S:EDh) CCAP4L (S:EEh) PCA Low Byte Compare/Capture Module n Register (n = 0..4)
7 CCAPnL 7 Bit Number 7-0 6 CCAPnL 6 5 CCAPnL 5 4 CCAPnL 4 3 CCAPnL 3 2 CCAPnL 2 1 CCAPnL 1 0 CCAPnL 0
Bit Mnemonic Description CCAPnL 7 Low byte of EWC-PCA comparison or capture values -0
Reset Value = 0000 0000b
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Table 55. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n = 0..4)
7 Bit Number 7 6 ECOMn 5 CAPPn 4 CAPNn 3 MATn 2 TOGn 1 PWMn 0 ECCFn
Bit Mnemonic Description Reserved The Value read from this bit is indeterminate. Do not set this bit. Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and the WatchDog Timer (WDT). Capture Mode (Positive) Module x bit Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin Capture Mode (Negative) Module x bit Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. Match Module x bit Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt. Toggle Module x bit The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. Pulse Width Modulation Module x Mode bit Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. Enable CCFx Interrupt bit Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request.
6
ECOMn
5
CAPPn
4
CAPNn
3
MATn
2
TOGn
1
PWMn
0
ECCFn
Reset Value = X000 0000b
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Table 56. CH Register CH (S:F9h) PCA Counter Register High value
7 CH 7 Bit Number 7-0 6 CH 6 5 CH 5 4 CH 4 3 CH 3 2 CH 2 1 CH 1 0 CH 0
Bit Mnemonic Description CH 7 - 0 High byte of Timer/Counter
Reset Value = 0000 00000b Table 57. CL Register CL (S:E9h) PCA counter Register Low value
7 CL 7 Bit Number 7-0 6 CL 6 5 CL 5 4 CL 4 3 CL 3 2 CL 2 1 CL 1 0 CL 0
Bit Mnemonic Description CL0 7 - 0 Low byte of Timer/Counter
Reset Value = 0000 00000b
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Analog-to-Digital Converter (ADC)
This section describes the on-chip 10 bit analog-to-digital converter of the T89C51AC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded potentiometric ADC. Two kinds of conversions are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended.
Features
* * * * * * * * * *
8 channels with multiplexed inputs 10-bit cascaded potentiometric ADC Conversion time 16 micro-seconds (typ.) Zero Error (offset) 2 LSB max Positive External Reference Voltage Range (VREF) 2.4 to 3.0V (typ.) ADCIN Range 0 to 3V Integral non-linearity typical 1 LSB, max. 2 LSB Differential non-linearity typical 0.5 LSB, max. 1 LSB Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock
ADC Port1 I/O Functions
Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register defines which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alternate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect.
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Figure 44. ADC Description
ADCON.5 ADCON.3
ADEN
ADSST
ADCON.4
ADC CLOCK
ADEOC
CONTROL
ADC Interrupt Request EADC
IEN1.1
AN0/P1.0 AN1/P1.1 AN2/P1.2 AN3/P1.3 AN4/P1.4 AN5/P1.5 AN6/P1.6 AN7/P1.7
000 001 010 011 100 101 110 111
AVSS
ADCIN
8
+ SAR 2
ADDH ADDL
Sample and Hold R/2R DAC
10
SCH2
ADCON.2
SCH1
ADCON.1
SCH0
ADCON.0
VAREF VAGND
Figure 45 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the "AC Characteristics" Sectionof the T89C51AC2 datasheet. Figure 45. Timing Diagram CLK ADEN
TSETUP
ADSST
TCONV
ADEOC
Note: Tsetup min = 4 us Tconv = 11 clock ADC = 1sample and hold + 10 bit conversion The user must ensure that 4 s minimum time between setting ADEN and the start of the first conversion.
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ADC Converter Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occurs when flag ADEOC is set (see Figure 47). Clear this flag for rearming the interrupt. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 58. Selected Analog Input
SCH2 0 0 0 0 1 1 1 1 SCH1 0 0 1 1 0 0 1 1 SCH0 0 1 0 1 0 1 0 1 Selected Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note that ADCIN should not exceed VAREF absolute maximum range! (see the "ACDC" section)
Clock Selection
The ADC clock is the same as CPU. The maximum clock frequency for ADC is 700 kHz. A prescaler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
Figure 46. A/D Converter Clock
CPU CLOCK
/2
Prescaler ADCLK
ADC Clock
A/D Converter
CPU Core Clock Symbol
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ADC Standby Mode IT ADC Management
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1 W. An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 47. ADC interrupt structure
ADEOC
ADCON.2
ADCI EADC
IEN1.1
Routine Examples
1. Configure P1.2 and P1.3 in ADC channels:
// configure channel P1.2 and P1.3 for ADC ADCF = 0Ch
// Enable the ADC ADCON = 20h
2. Start a standard conversion:
// The variable "channel" contains the channel to convert // The variable "value_converted" is an unsigned int // Clear the field SCH[2:0] ADCON and= F8h // Select channel ADCON |= channel // Start conversion in standard mode ADCON |= 08h // Wait flag End of conversion while((ADCON and 01h)!= 01h) // Clear the End of conversion flag ADCON and= EFh // read the value value_converted = (ADDH << 2)+(ADDL)
3. Start a precision conversion (need interrupt ADC):
// The variable "channel" contains the channel to convert // Enable ADC EADC = 1 // clear the field SCH[2:0] ADCON and= F8h // Select the channel ADCON |= channel // Start conversion in precision mode ADCON |= 48h
Note:
To enable the ADC interrupt: EA = 1
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Registers
Table 59. ADCF Register ADCF (S:F6h) ADC Configuration
7 CH 7 Bit Number 6 CH 6 5 CH 5 4 CH 4 3 CH 3 2 CH 2 1 CH 1 0 CH 0
Bit Mnemonic Description Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port.
7-0
CH 0:7
Reset Value = 0000 0000b Table 60. ADCON Register ADCON (S:F3h) ADC Control Register
7 Bit Number 7 6 PSIDLE 5 ADEN 4 ADEOC 3 ADSST 2 SCH2 1 SCH1 0 SCH0
Bit Mnemonic Description Pseudo Idle mode (best precision) Set to put in idle mode during conversion. Clear to convert without idle mode. Enable/Standby Mode Set to enable ADC. Clear for Standby mode (power dissipation 1 uW). End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. Start and Status Set to start an A/D conversion. Cleared by hardware after completion of the conversion. Selection of channel to convert See Table 58.
6
PSIDLE
5
ADEN
4
ADEOC
3
ADSST
2-0
SCH2:0
Reset Value = X000 0000b
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Table 61. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler
7 Bit Number 7-5 6 5 4 PRS 4 3 PRS 3 2 PRS 2 1 PRS 1 0 PRS 0
Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler fADC = fcpu clock/ (4 (or 2 in X2 mode)* (PRS +1)).
4-0
PRS4:0
Reset Value = XXX0 0000b Table 62. ADDH Register ADDH (S:F5h Read Only) ADC Data High byte register
7 ADAT 9 Bit Number 7-0 6 ADAT 8 5 ADAT 7 4 ADAT 6 3 ADAT 5 2 ADAT 4 1 ADAT 3 0 ADAT 2
Bit Mnemonic Description ADAT9:2 ADC result bits 9 - 2
Reset Value = 00h Table 63. ADDL Register ADDL (S:F4h Read Only) ADC Data Low byte register
7 Bit Number 7-2 6 5 4 3 2 1 ADAT 1 0 ADAT 0
Bit Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. ADC result bits 1-0
1-0
ADAT1:0
Reset Value = 00h
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Interrupt System
The controller has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1 and 2), a serial port interrupt, a PCA, a timer overrun interrupt and an ADC. These interrupts are shown below.
Figure 48. Interrupt Control System
INT0# External Interrupt 0 EX0
IEN0.0
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Highest Priority Interrupts
Timer 0 ET0
IEN0.1
INT1#
External Interrupt 1 EX1
IEN0.2
Timer 1 ET1 CEX0:5
IEN0.3
PCA EC
TxD RxD
IEN0.6
UART ES
IEN0.4
Timer 2 ET2
IEN0.5
00 01 10 11
AIN1:0
A to D Converter EADC
IEN1.1
00 01 10 11
Interrupt Enable
Priority Enable
Lowest Priority Interrupts
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Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination. Table 64. Priority Level Bit Values
IPH.x 0 0 1 1 IPL.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, see Table 65. Table 65. Interrupt Priority Within Level
Interrupt Name external interrupt (INT0) Timer0 (TF0) external interrupt (INT1) Timer1 (TF1) PCA (CF or CCFn) UART (RI or TI) Timer2 (TF2) ADC (ADCI) Interrupt Address Vector 0003h 000Bh 0013h 001Bh 0033h 0023h 002Bh 0043h Priority Number 1 2 3 4 5 6 7 9
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Registers
Table 66. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register
7 EA Bit Number 6 EC 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Bit Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. Timer 2 overflow interrupt Enable bit Clear to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0.
7
EA
6
EC
5
ET2
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Reset Value = 0000 0000b bit addressable
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Table 67. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register
7 Bit Number 7 6 5 4 3 2 1 EADC 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt.
6
-
5
-
4
-
3
-
1
EADC
Reset Value = xxxx x000b bit addressable
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Table 68. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register
7 Bit Number 7 6 PPC 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority bit Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. Serial port Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level.
6
PPC
5
PT2
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Reset Value = X000 0000b bit addressable
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Table 69. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1
7 Bit Number 7 6 5 4 3 2 1 PADCL 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Priority level less significant bit. Refer to PSPIH for priority level.
6
-
5
-
4
-
3
-
1
PADCL
Reset Value = XXXX X000b bit addressable
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Table 70. IPL0 Register IPH0 (B7h) Interrupt High Priority Register
7 Bit Number 7 6 PPCH 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority level most significant bit PPCH PPC Priority level 0 0 Lowest 0 1 1 0 1 1 Highest priority Timer 2 overflow interrupt High Priority bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial port High Priority bit PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt High Priority bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 High Priority bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt High Priority bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 high priority bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest
6
PPCH
5
PT2H
4
PSH
3
PT1H
2
PX1H
1
PT0H
0
PX0H
Reset Value = X000 0000b
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Table 71. IPH1 Register IPH1 (S:F7h) Interrupt high priority Register 1
7 Bit Number 7 6 5 4 3 2 1 PADCH 0 -
Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Priority level most significant bit PADCH PADCL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest
6
-
5
-
4
-
3
-
1
PADCH
Reset Value = XXXX X000b
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Electrical Characteristics
Absolute Maximum Ratings
Ambiant Temperature Under Bias: I = industrial ....................................................... -40C to 85C Storage Temperature .................................... -65C to + 150C Voltage on VCC from VSS ......................................-0.5V to + 6V Voltage on Any Pin from VSS .................... -0.5V to VCC + 0.2 V Power Dissipation .......................................................... 1 W(2) Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package.
DC Parameters for Standard Voltage
TA = -40C to +85C; VSS = 0V; VCC = 5V 10%; F = 0 to 40 MHz Table 72. DC Parameters in Standard Voltage
Symbol VIL VIH VIH1 Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ(5) Max 0.2Vcc - 0.1 VCC + 0.5 VCC + 0.5 0.3 VOL Output Low Voltage, ports 1, 2, 3 and 4(6) 0.45 1.0 0.3 VOL1 Output Low Voltage, port 0, ALE, PSEN
(6)
Unit V V V V V V V V V V V V
Test Conditions
IOL = 100 A(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOL = 200 A(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) IOH = -10 A IOH = -30 A IOH = -60 A V CC = 5V 10% IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA V CC = 5V 10%
0.45 1.0 VCC - 0.3
VOH
Output High Voltage, ports 1, 2, 3, 4 and 5
VCC - 0.7 VCC - 1.5
VCC - 0.3 VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.7 VCC - 1.5 RRST IIL ILI ITL CIO IPD RST Pulldown Resistor Logical 0 Input Current ports 1, 2, 3 and 4 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 and 4 Capacitance of I/O Buffer Power down Current 160 20 40 200 -50 10 -650
V V V k A A A pF A
Vin = 0.45V 0.45V < Vin < VCC Vin = 2.0V Fc = 1 MHz TA = 25C 4.5V < VCC < 5.5V(3)
10 350
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Table 72. DC Parameters in Standard Voltage (Continued)
Symbol Parameter Power Supply Current Min Typ(5) Max Unit Test Conditions
ICCOP = 0.7 Freq (MHz) + 3 mA ICCIDLE = 0.6 Freq (MHz) + 2 mA Vcc = 5.5V
(1) (2)
ICC
Notes:
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 52), VIL = VSS + 0.5V, VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 49). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = V SS (see Figure 50). 3. Power down ICC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = V SS (see Figure 51). In addition, the WDT must be inactive and the POF flag must be set. 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
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Figure 49. ICC Test Condition, Active Mode
VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC
Figure 50. ICC Test Condition, Idle Mode
VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
Figure 51. ICC Test Condition, Power-down Mode
VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC
Figure 52. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1
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DC Parameters for A/D Converter
Table 73. DC Parameters for AD Converter in Precision conversion
Symbol Parameter AVin Rref Vref Cai INL DNL OE Analog input voltage Resistance between Vref and Vss Reference voltage Analog input Capacitance Integral non-linearity Differential non-linearity Offset error -2 Min Vss- 0.2 12 2.40 60 1 0.5 2 1 2 16 Typ(1) Max Unit V k V pF During sampling lsb lsb lsb Test Conditions
Vref + 0.2
24 3.00
Notes:
1. Typicals are based on a limited number of samples and are not guaranteed.
AC Parameters
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40C to +85C; VSS = 0V; V CC = 5V 10%; F = 0 to 40 MHz. TA = -40C to +85C; VSS = 0V; V CC = 5V 10%. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table 74, Table 77 and Table 80 give the description of each AC symbols. Table 75, Table 78 and Table 81 give for each range the AC parameter. Table 76, Table 79 and Table 82 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use this value in the formula. Example: TLLIV and 20 MHz, Standard clock. x = 30 ns T = 50 ns TCCIV = 4T - x = 170 ns
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External Program Memory Characteristics
Table 74. Symbol Description
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Parameter Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instruction In PSEN Low to Address Float
Table 75. AC Parameters for a Fix Clock (F = 40 MHz)
Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 18 85 10 15 55 35 Min 25 40 10 10 70 Max Units ns ns ns ns ns ns ns ns ns ns ns ns
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Table 76. AC Parameters for a Variable Clock
Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x X parameter 10 15 15 30 10 20 40 0 7 40 10 Units ns ns ns ns ns ns ns ns ns ns ns
External Program Memory Read Cycle
12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ
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External Data Memory Characteristics
Table 77. Symbol Description
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high
Table 78. AC Parameters for a Variable Clock (F = 40 MHz)
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH 10 50 75 10 160 15 0 40 0 30 160 165 100 Min 130 130 100 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 79. AC Parameters for a Variable Clock
Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x X parameter 20 20 25 0 20 40 60 25 25 25 15 25 10 0 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
External Data Memory Write Cycle
ALE TWHLH
PSEN
TLLWL
TWLWH
WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX
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External Data Memory Read Cycle
ALE TLLDV TWHLH
PSEN
TLLWL
TRLRH
RD TAVDV TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDX DATA IN
TRHDZ
Serial Port Timing - Shift Register Mode
Table 80. Symbol Description (F= 40 MHz)
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Table 81. AC Parameters for a Fix Clock (F= 40 MHz)
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Min 300 200 30 0 117 Max Units ns ns ns ns ns
Table 82. AC Parameters for a Variable Clock
Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x 50 20 0 133 X parameter for -M range Units ns ns ns ns ns
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Shift Register Timing Waveforms
INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV
VALID VALID
0
1
2
3
4
5
6
7
8
TXHQX 1 2 TXHDX
VALID VALID VALID VALID VALID
3
4
5
6
7 SET TI
VALID
SET RI
External Clock Drive Characteristics (XTAL1)
Table 83. AC Parameters
Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 25 5 5 5 5 60 Max Units ns ns ns ns ns %
External Clock Drive Waveforms
VCC-0.5V 0.45V
0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH
AC Testing Input/Output Waveforms
INPUT/OUTPUT
VCC -0.5V 0.45V
0.2 VCC + 0.9 0.2 VCC - 0.1
AC inputs during testing are driven at VCC - 0.5 for a logic "1" and 0.45V for a logic "0". Timing measurements are made at VIH min for a logic "1" and V IL max for a logic "0". Float Waveforms
FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V
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For timing purposes as the port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/V OL level occurs. IOL/I OH 20mA. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
INTERNAL
CLOCK XTAL2 ALE
STATE4 P1 P2
STATE5 P1 P2
STATE6 P1 P2
STATE1 P1 P2
STATE2 P1 P2
STATE3 P1 P2
STATE4 P1 P2
STATE5 P1 P2
EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE RD PCL OUT DATA SAMPLED FLOAT INDICATES ADDRESS TRANSITIONS
THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION
PCL OUT
DATA SAMPLED FLOAT
PCL OUT
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
DATA SAMPLED FLOAT
P2 WRITE CYCLE
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WR P0
DPL OR Rt OUT DATA OUT P2
PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM MEMORY IS EXTERNAL
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED OLD DATA NEW DATA P0 PINS SAMPLED P0 PINS SAMPLED
RXD SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
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Flash Memory Table 84. Timing Symbol Definitions
Signals S (Hardware condition) PSEN#,EA R B RST FBUSY flag Conditions L V X Low Valid No Longer Valid
Table 85. Memory AC Timing VDD = 5V +/- 10% , TA = -40 to +85C
Symbol TSVRL TRLSX TBHBL Parameter Input PSEN# Valid to RST Edge Input PSEN# Hold after RST Edge Flash Internal Busy (Programming) Time Min 50 50 10 Typ Max Unit ns ns ms
Figure 53. Flash Memory - ISP Waveforms
RST TSVRL PSEN#1 TRLSX
Figure 54. Flash Memory - Internal Busy Waveforms
FBUSY bit TBHBL
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Ordering Information
Table 86. Possible Order Entries
Part Number T89C51AC2-RLTIM T89C51AC2-SLSIM Memory Size 32K bytes 32K bytes Supply Voltage 5V + 10% 5V + 10% Temperature Range Industrial Industrial Max Frequency 40 MHz 40 MHz Package VQFP44 PLCC44 Packing Tray Stick
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Package Drawings
VQFP 44
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Package Drawings
PLCC44
110
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Table of Contents
Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 2 Pin Configuration .................................................................................. 3
I/O Configurations................................................................................................. Port 1, Port 3 and Port 4 ....................................................................................... Port 0 and Port 2................................................................................................... Read-Modify-Write Instructions ............................................................................ Quasi-bi-directional Port Operation ...................................................................... 6 6 7 8 9
SFR Mapping ....................................................................................... 10 Clock .................................................................................................... 14
Description.......................................................................................................... 14 Register .............................................................................................................. 17
Power Management ............................................................................ 18
Reset .................................................................................................................. 18 Reset Recommendation to Prevent Flash Corruption ........................................ 18 Idle Mode .............................................................................................................19 Power-down Mode.............................................................................................. 19 Registers..............................................................................................................21
Data Memory ....................................................................................... 22
Internal Space......................................................................................................23 External Space ................................................................................................... 24 Dual Data Pointer ............................................................................................... 25 Registers..............................................................................................................27
EEPROM Data Memory ....................................................................... 29
Write Data in the Column Latches ...................................................................... Programming ...................................................................................................... Read Data........................................................................................................... Examples ............................................................................................................ Registers............................................................................................................. 29 29 29 30 31
Program/Code Memory ...................................................................... 32
External Code Memory Access .......................................................................... 32 Flash Memory Architecture................................................................................. 34 Overview of FM0 Operations .............................................................................. 35 Registers..............................................................................................................41
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In-System Programming (ISP) ........................................................... 42
Flash Programming and Erasure ........................................................................ Boot Process ...................................................................................................... Application Programming Interface..................................................................... XROW Bytes....................................................................................................... Hardware Security Byte ...................................................................................... 42 43 44 45 46
Serial I/O Port ...................................................................................... 47
Framing Error Detection .................................................................................... 47 Automatic Address Recognition.......................................................................... 48 Given Address ..................................................................................................... 49 Broadcast Address ............................................................................................. 49 Registers............................................................................................................. 50
Timer/Counters ................................................................................... 53
Timer/Counter Operations .................................................................................. Timer 0................................................................................................................ Timer 1................................................................................................................ Interrupt .............................................................................................................. Registers............................................................................................................. 53 53 55 57 58
Timer 2 ................................................................................................. 62
Auto-reload Mode ............................................................................................... 62 Programmable Clock-output ............................................................................... 63 Registers............................................................................................................. 64
WatchDog Timer ................................................................................. 67
WatchDog Programming .................................................................................... 68 WatchDog Timer During Power down Mode and Idle......................................... 69
Programmable Counter Array (PCA) ................................................ 71
PCA Timer .......................................................................................................... 71 PCA Modules...................................................................................................... 72 PCA Interrupt ...................................................................................................... 73 PCA Capture Mode............................................................................................. 73 16-bit Software Timer Mode ............................................................................... 74 High Speed Output Mode ....................................................................................75 Pulse Width Modulator Mode.............................................................................. 75 PCA WatchDog Timer ........................................................................................ 76 PCA Registers ..................................................................................................... 77
Analog-to-Digital Converter (ADC) .................................................... 82
Features.............................................................................................................. ADC Port1 I/O Functions .................................................................................... ADC Converter Operation................................................................................... Voltage Conversion ............................................................................................ 82 82 84 84
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Clock Selection ................................................................................................... 84 ADC Standby Mode ............................................................................................ 85 IT ADC Management .......................................................................................... 85 Routine Examples............................................................................................... 85 Registers..............................................................................................................86
Interrupt System ................................................................................. 88
Registers............................................................................................................. 90
Electrical Characteristics ................................................................... 96
Absolute Maximum Ratings ................................................................................ DC Parameters for Standard Voltage ................................................................. DC Parameters for A/D Converter ...................................................................... AC Parameters ................................................................................................... 96 96 99 99
Ordering Information ........................................................................ 108 Package Drawings ............................................................................ 109
VQFP 44 ........................................................................................................... 109
Package Drawings ............................................................................ 110
PLCC44 ............................................................................................................ 110
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